Integrated circuits comprise many transistors and the electrical interconnections between them. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty to design an integrated circuit. An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers is determined by the concentration of dopants within the area. In turn, these distinct areas interact with one another to form transistors, diodes, and other electronic devices. These specific transistors and other devices may interact with each other by field interactions or by direct electrical interconnections. Openings or windows are created for electrical connections between the layers by a combination of masking, layering, and etching additional materials on top of the wafers. These electrical interconnections may be within the semiconductor or may lie above the semiconductor areas and layers using a complex mesh of conductive layers, usually of metal such as aluminum, tungsten, or copper fabricated by deposition on the surface and selective removal, leaving the electrical interconnections. Insulative layers, e.g., silicon dioxide, may separate any of these semiconductor or connectivity layers.
Integrated circuits and chips have become increasingly complex, with the speed and capacity of chips doubling about every eighteen months. This increase has resulted from advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to specify and design a chip that performs as actually specified. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application. The demand for complex custom-designed chips increase with the increasing variety of microprocessor-driven applications and products, yet the time and money required to design chips have become a bottleneck in the time it takes to bring these products to market. Without an assured successful outcome within a specified time, the risks have risen along with costs and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
The challenge of complexity has been met by introducing more powerful specialized software tools intended to design chips correctly and efficiently. As the software tools evolve, however, the tools themselves have become increasingly complex requiring more time to master and use them. Correspondingly, the cost of staffing, training, and coordinating the various aspects of chip design has also increased. One general response to this dilemma has been a call for what are termed “higher levels of abstraction,” which simply means that the logical entities with which designers work are standardized, encapsulated, and bundled together so they can be treated like black box functions. This abstraction has characterized the semiconductor industry throughout its history. Today, however, the software tools used in chip design are so complex that it is difficult to adapt them to this higher level of abstraction. Coordinating these realms of complexity is a challenge in the design and fabrication of a custom chip. Customer needs and specifications must be aligned with tools and capabilities of both designers and fabrication facilities. Each fabrication facility, for example, operates with design rules, equipment, molds, recipes and standards that have myriad implications for the final work and must be considered early in the process.
Meanwhile, several types of chips have been developed that take advantage of this modular approach; they are partly fixed and partly programmable/customizable. The utility of these chips is limited by factors such as complexity, cost, time, and design constraints. The field programmable gate array (FPGA) refers to type of logic chip that can be reprogrammed. Because of the programmable features, FPGAs are flexible and modification is almost trivial. FPGAs, however, are very expensive and have the largest die size. The disadvantage of FPGAs, moreover, is their relatively high cost per function, relatively low speed, and high power consumption. FPGAs are used primarily for prototyping integrated circuit designs, and once the design is set, faster hard-wired chips are produced. Programmable gate arrays (PGAs) are also flexible in the numerous possible applications that can be achieved but not quite as flexible as the FPGAs, and are more time-consuming to modify and test. An application specific integrated circuit (ASIC) is another type of chip designed for a particular application. ASICs are efficient in use of power compared to FPGAs, and are quite inexpensive to manufacture at high volumes. ASICs, however, are very complex to design and prototype because of their speed and quality. Application Specific Standard Products (ASSPs) are hard-wired standard chips that meet a specific need, but this customization is both time-consuming and costly. An example of an ASSP might be a microprocessor in a heart pacemaker.
As an example, most ASICs today have an embedded or external central processing unit (CPU) connected internally to registers and memory, either on or off-chip. These registers and memories are read and written by the CPU through memory-mapped accesses and can be physically arranged and spread throughout the chip in many modules, some of which may be logically hierarchical. Documenting, implementing, connecting, and testing these registers and internal memories is extremely time consuming and prone to errors. Chip designers and testers define the specification and address map for registers and internal memory, the register transfer logic (RTL) implementation, the verification testcases, and the firmware header file all in separate and manual tasks. This approach is time consuming, tedious, and prone to errors created by manual editing.
There is thus a need in the industry to increase the flexibility of the design process of the integrated circuits yet at the same time reduce the cost of each individual design.